Silicon and carbon have a diamond crystal structure. The lattice constant of silicon is about 0.543095 nm at 300 K, and the lattice constant of carbon is about 0.356683 nm at 300 K. A Si:C region, or a carbon substituted silicon region, is a crystalline alloy of silicon and carbon in which carbon atoms occupy substitutional sites in a silicon lattice at an atomic concentration which is typically less than 5%. The Si:C region has the diamond crystal structure at a lattice constant between the lattice constant of silicon and the lattice constant of carbon.
For a carbon atomic concentration range less than 3%, high quality single crystalline Si:C regions may be formed epitaxially on a single crystalline silicon substrate as an embedded region. Such embedded Si:C regions may be employed to exert tensile stress on the surrounding portions of the silicon substrate so that silicon devices built in proximity to the embedded Si:C regions may benefit from the tensile stress generated by the embedded Si:C regions. For example, n-type field effect transistors built in a semiconductor substrate may have enhanced performance through the increase in electron mobility along some crystalline orientations under tensile stress generated by embedded Si:C regions. Typical embedded Si:C regions include embedded Si:C containing source and drain regions.
Referring to FIG. 1, an exemplary prior art semiconductor comprises a silicon substrate 108 and semiconductor structures thereupon. Specifically, the exemplary prior art semiconductor structure comprises a nested device region N and an isolated device region I. The nested device region N comprises an array of nested gate lines separated by a distance comparable to the gate length of the gate lines in the nested device region N. Each gate line in the nested device region N comprises a vertical stack of a gate dielectric 130, a gate electrode 132, and a dielectric gate cap portion 133. The width of a gate dielectric 130 in the nested device region N in the vertical cross-sectional view of FIG. 1 is the gate length of the corresponding gate line. The isolated device region I comprises an isolated gate line separated from other gate lines or other protruding structures by a distance greater than several times the length of the gate line in the isolated device region. The gate line in the isolated device region I comprises a vertical stack of a gate dielectric 130, a gate electrode 132, and a dielectric gate cap portion 133. The width of the gate dielectric 130 in the isolated device region I in the vertical cross-sectional view in FIG. 1 is the gate length of the gate line in the isolated device region I.
Gate spacers 134 are formed on the sidewalls of gate lines (130, 132, 133) by conformal deposition of a dielectric layer, followed by an anisotropic etch that removed horizontal portions of the dielectric layer. The remaining vertical portions of the dielectric layer constitute the gate spacers 134.
Trenches are formed in the silicon substrate 108 and filled with embedded Si:C regions by selective epitaxy. Specifically, nested embedded Si:C regions 140N are formed in the nested device region N, and isolated embedded Si:C regions 140I are formed in the isolated device region I. Due to pattern dependent growth rate of selective epitaxy process that forms the embedded Si:C regions (140N, 140I), the thickness of Si:C material deposited in the nested embedded Si:C regions 140N is different from the thickness of the material deposited in the isolated embedded Si:C regions 140I. Specifically, the thickness of the Si:C material deposited in the nested embedded Si:C regions 140N, which is herein referred to as a nested embedded Si:C region thickness tn′, is less than the thickness of the Si:C material deposited in the isolated embedded Si:C regions 140I, which is herein referred to as an isolated embedded Si:C region thickness ti′. The ratio of the isolated embedded Si:C region thickness ti′ to the nested embedded Si:C region thickness tn′ is greater than 1 when the dimensions of the gate lines (130, 132, 133) are the same across the nested device region N and the isolated device region I. While the ratio of the isolated embedded Si:C region thickness ti′ to the nested embedded Si:C region thickness tn′ depends on the dimensions of the gate lines (130, 132, 133) and processing parameters of the selective Si:C deposition process, the ratio is consistently substantially greater than 1 and is in the range from about 1.3 to about 1.9, and typically from about 1.45 to about 1.75.
Such differences between the isolated embedded Si:C region thickness ti′ to the nested embedded Si:C region thickness tn′ cause differences in the height of embedded Si:C containing source and drain regions across the nested device region N and the isolated device region I, and result in differences in device performance between field effect transistors in nested configuration and field effect transistors in isolation. In general, device parameters of an arbitrary field effect transistor having a set of intrinsic device parameters such as a gate length, a gate width, and a dopant profile become layout dependent due to the variability of the thickness of embedded Si:C regions depending on other devices located in proximity to the field effect transistor. Such layout dependency in performance increases variability in device parameters complicating design of a circuit and prediction of circuit performance by simulation.
In view of the above, there exists a need for a method for forming Si:C containing regions in a silicon substrate in which the thickness of the Si:C containing regions is substantially independent of the layout of surrounding structures, i.e., the thickness of the Si:C containing regions is substantially pattern-independent.